Project: FPGA-Based Test Acceleration Methodology for Complex Electronic Boards

The general objective of the COMBOARD project is to create a universal, complementary technique for system-level testing of structural defects applicable at the system assembly phase as well as later in the field for COtenance and diagnostics of complex electronic boards. _x000D_The new technique proposed in COMBOARD will be complementary to the standard Boundary Scan (BS) test while dramatically extending the BS applicability for modern complex on-board data transfer buses and protocols. The technology is based on combination of JTAG port for test data transport and programmable logic devices (FPGA, CPLD, etc) for test data processing. Both needed components are massively available on contemporary system boards (PCBs). The technology will also be synchronized with BS and can be included into the standard BS test flow._x000D_Accordingly to our estimation COMBOARD technology will accelerate the speed of single tests 50-100 times. This claim is confirmed by the experiments based on a simple FPGA-based ad-hoc technique. The first promising results were presented and published at International Test Conference (ITC'2009) in Austin, TX. They are also referenced in annexes to this project proposal. As the result, depending on the specific device, the whole testing session shall become 2-10 times faster. Using BS paired with COMBOARD technique, one can potentially avoid functional tests, which would bring about 40-45% test costs reduction. COMBOARD will yield better fault coverage compared to BS by covering parametric faults (wrong resistor values, wrong wire dimensions or routing, missing termination, cross-talk, etc.)._x000D_The technique would also increase the speed of in-system programming (ISP) of e.g. flash memories and other tasks that are traditionally performed using BS. By using COMBOARD, the speed of ISP will be in average increased up to 2 orders of magnitude._x000D_During the last decade the evolution of electronic systems has made a major leap. Complex multilayer boards densely stuffed with highly integrated components have become the state of the art in the consumer electronics such as mobile phones, digital cameras, personal computers, etc. On one hand, this trend allows designing “smarter”, more compact and power-efficient devices that improve the human’s quality of life. On the other hand, it influences in a negative way both the reliability and testability of modern electronic systems._x000D_The electronic manufacturing industry is entering a new age, where static structural test technologies like BS and in-circuit test (ICT) start quickly losing their efficiency in terms of fault coverage, while there is currently no existing systematic alternative that can replace them. Despite of constantly improving test automation solutions, the new technological reality elevates the cost of testing in terms of extra engineering efforts and design-for-testability (DFT) overhead. This situation brings up a lot of concerns in the industry and needs a due attention from academic researchers._x000D_The product quality has a direct impact on the consumer’s satisfaction and manufacturer’s reputation. Hence the quality assurance including testing for manufacturing defects constitutes a large portion of production costs. As a result, the sector of test and measurement instrumentation and automation represents an attractive market with high profit margins. The importance of this sector is further confirmed by blossoming activity of large industrial players and academic researchers in the field of system debug (NEXUS, MIPI, IEEE 1149.7) and test standards (IEEE P1687 IJTAG, SJTAG, IEEE 1500)._x000D_The general objective of the project is realised by setting following specific measurable objectives:_x000D_• Developing FPGA-based test access mechanism (TAM) for static and dynamic (at-speed/high-speed) testing;_x000D_• Developing methods for converting a JTAG port into a high-performance communication port;_x000D_• Developing test automation algorithms based on the new TAM and solving issue of synchronisation with BS._x000D_The consortium of the project will consist of an Estonian R&D company Testonica Lab specialised in design automation related to electronic systems test and a mid-size German company GOEPEL electronic GmbH, a worldwide leading vendor of innovative test and measurement equipment, accompanied by comprehensive product support and value added services. Deeper FPGA competence will be outsourced to Tallinn University of Technology. (See also section 2.4.1)_x000D_The results of the project (listed in section 2.2.3) will be included into the test automation toolkit of GOEPEL electronic, which is a global test equipment vendor. In this way, the results of the project will be made immediately available in the form of a specific product on a global market. The developed solution will be competing on the markets of boundary scan and functional test tools. (See section 2.3 for detailed market analysis).

Acronym COMBOARD (Reference Number: 5568)
Duration 01/04/2011 - 31/08/2012
Project Topic The objective of the project is to develop a fast universal system-level test access and at-speed test application framework for complex electronic boards that is based on industry standard JTAG interface,targets manufacturing testing and in-system programming,and can be integrated into BS test flow
Project Results
(after finalisation)
We have jointly developed a new technology that combines a new type of embedded instrumentation and software framework that accelerates test and programming of boards based on Field Programmable Gate Arrays (FPGA). The entire development was verified in the lab and by extended customer trials. The output of project are demo vehicles and prototypes which need now transformation into final products to start the sales activities. _x000D_
Network Eurostars
Call Eurostars Cut-Off 4

Project partner

Number Name Role Country
2 Testonica Lab OÜ Coordinator Estonia
2 Goepel electronic GmbH Partner Germany