Project: Integrated Circuit Noise Analysis and Optimisation Framework
IC-NAO aims at seizing a major market opportunity by developing new design tools for microchips. The technology developed will address physical-level effects early in the design flow. By early analysis and design optimisation, integrated circuits (ICs) can be made robust to fabrication drawbacks, improving physical design convergence. The IC-NAO solution will be applied to complex microchips, so called Systems-on-Chip (SoC), which is the established model for the design of advanced ICs. In particular, mixed-signal designs will be addressed and a mixed-signal demonstrator IC will be fabricated._x000D__x000D_Goal and potential_x000D_Electrical noise poses an increasing challenge in the design of SoCs due to two trends: faster switching of on-chip signals causes steeper current slopes resulting in an increased di/dt noise; and larger circuits result in an increasing accumulated noise across a single IC. The noise problem is particularly challenging in mixed-signal SoC designs which incorporate noisy digital design blocks together with noise sensitive analog blocks._x000D__x000D_The overall goal of IC-NAO is the development of key components of an IC design framework (CAD software and IC design methods) and its integration into existing COstream IC design flows. Such a design framework will implement a chip-level analysis and optimisation technology, which solves major electrical noise problems in the IC design industry. To reach the overall goal, the following has to be achieved: _x000D_1) Development of two power noise analysis software engines enabling _x000D_a. annotation of Register Transfer Level (RTL) simulations unto a design netlist, for easy access to simulation-based analysis, and_x000D_b. advanced vectorless analysis, for high quality results without the need for simulations; _x000D_2) Development of RTL methods for noise-oriented design partitioning and conditioning, to leverage advanced noise optimisation methods; _x000D_3) Development of ultra-high performance power delivery network (PDN) analysis software that enables advanced optimisation methods and inclusion of IC package models; and _x000D_4) Integration of these developments in an existing IC design tool to leverage a base of support for standard formats and visualisation._x000D__x000D_The market potential of IC-NAO solution is very large. The global SoC market is already considerable and continually expanding. Meanwhile, SoC fabrication technologies are becoming more sensitive to noise, and the analysis and optimisation technology to be developed in IC-NAO delivers considerable benefits related to physical design closure. The primary market for the IC-NAO solution is the EDA (Electronic Design Automation) tools and semiconductor IP market, which has reached €4,8B in 2011. The sub-segment of IC Power Analysis and Optimisation, within which the IC-NAO technology belongs, is one of the fastest growing sub-segments of EDA, having had an average growth of 14% per year since 2000. _x000D__x000D_Background_x000D_Geometry scaling of microchips, according to Moore’s law, has led to a doubling of processing resources on a single chip every second year. Scaling transistor sizes means higher performance and integration and lower power usage, thus allowing for better performance and lower cost of consumer products. However, scaling has several associated drawbacks and challenges, such as increased leakage current, power density, on-chip noise, wire resistance, parametric process variability and design complexity. To ensure a safe bridge across these challenges, automated tools and new methods are required for counteracting the drawbacks. IC-NAO addresses the deployment of such methods and the development of tools to support it._x000D__x000D_The consortium_x000D_The IC-NAO consortium is focused on a Danish SME, Teklatech, as the instigator of the idea and holder of key knowledge and relevant IPR. To mature the technology and secure market uptake, a close cooperation between developers and end-users is necessary, as well as a broader link into the technology market. In the consortium, priority has thus been given to full vertical value chain integration. _x000D__x000D_IHP, from Germany, is a leading-edge European Research and Innovation Center for wireless communication technologies. It has worked in SoC noise optimisation for many years, and will provide valuable input for design methodology. IHP will also develop new methods for RTL-stage circuit noise analysis and design partitioning, and perform the frontend design work on the demonstrator. IHP represents the frontend-user of the IC-NAO technology._x000D__x000D_RacyICs is a German mixed-signal SoC consultancy SME. By performing design work for major European semiconductor houses, they hold a broad knowledge of backend-level application issues relating to the use of the technology. Also, they hold knowhow in tool flow integration. IC-NAO will provide a design framework for RacyICs, further increasing the quality of their work. RacyICs is in a unique position to ensure that the IC-NAO technology is fit for general industry adaptation.
| Acronym | IC-NAO (Reference Number: 7531) |
| Duration | 01/10/2012 - 31/01/2015 |
| Project Topic | The IC-NAO project aims at seizing a major market opportunity for the participating SMEs and Ps in developing an innovative design tool for microchips. The technology will solve major problems caused by the continuous scaling of microchip technologies. |
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Project Results (after finalisation) |
For Teklatech, the CO results of the IC-NAO project have been concepts and prototypes of key software components to be matured and integrated into the electronic design automation software framework FloorDirector, which is our CO commercial product. _x000D__x000D_In particular, the following prototype components have been developed:_x000D_1) Components for power noise signature generation used in dynamic power analysis:_x000D_ a) logic propagation engine_x000D_ b) vectorless noise signature engine_x000D_2) Components for a power delivery network (PDN) analysis:_x000D_ a) package model analysis_x000D_ b) PDN reduction for fast analysis_x000D__x000D_Also, the results from the measurements of the prototype ICs are an important result, to be used during the marketing of our product._x000D_ |
| Network | Eurostars |
| Call | Eurostars Cut-Off 8 |
Project partner
| Number | Name | Role | Country |
|---|---|---|---|
| 3 | IHP GmbH - Innovations for High Performance Microelectronics Leibniz-Institut fuer innovative Mikroelektronik | Partner | Germany |
| 3 | RacyICs GmbH | Partner | Germany |
| 3 | Teklatech A/S | Coordinator | Denmark |